1. Field of the Invention
Embodiments of the present invention generally relate to a processor based hardware emulation engine and, more specifically, to a method and apparatus for synchronizing processors within the emulation engine.
2. Description of the Related Art
Hardware emulators are programmable devices used in the verification of hardware designs. A common method of hardware design verification is to use processor-based hardware emulators to emulate the design. These processor-based emulators sequentially evaluate combinatorial logic levels, starting at the inputs and proceeding to the outputs. Each pass through the entire set of logic levels is known as a cycle; the evaluation of each individual logic level is known as an emulation step.
An exemplary hardware emulator is described in commonly assigned U.S. Pat. No. 6,618,698 titled “Clustered Processors In An Emulation Engine”, which is hereby incorporated by reference in its entirety. Hardware emulators allow engineers and hardware designers to test and verify the operation of an integrated circuit, an entire board of integrated circuits, or an entire system without having to first physically fabricate the hardware.
The complexity and number of logic gates present on an integrated circuit has increased significantly in the past several years. Hardware emulators need to improve in efficiency to keep pace with the increased complexity of integrated circuits. The speed with which a hardware emulator can emulate an integrated circuit is one of the most important benchmarks of the emulator's efficiency, and also one of the emulator's most important selling factors in the emulator market.
A hardware emulator is comprised of multiple processors. During each process cycle, each processor is capable of emulating a logic gate, mimicking the function of a logic gate in an integrated circuit. The processors are arranged to compute results in parallel, in the same way logic gates present in an integrated circuit compute many results in parallel. This creates a chain of logic similar to what occurs in an integrated circuit. In the chain of logic, efficient communication between processors is crucial.
The programs executed by the processors in a hardware emulator consist of instructions containing a sequence of operations. The entire sequence of operations is known as a model. The model is further comprised of an unconditional model, i.e., a sequence of operations that are not dependent upon the outcome of any other sequence of operations, and one or more conditional models, i.e., a sequence of operations whose execution is dependent upon the outcome of another sequence of operations. The conditional and unconditional models are referred to herein as “submodels” with respect to the overall “model” of the hardware.
Certain operations act directly upon data, while other operations describe the conditions necessary for the data to be acted upon. For example, consider the conditional submodel described by the sequence of operations described by equation 1:if(a!=0) b=c+d   (1)The operation “b=c+d” (b equals c plus d) acts upon the data element “b” using “c” and “d” as operands. The operation “a !=0” (a does not equal zero) describes the condition necessary for data element “b” to be acted upon.
Conditional submodels were previously not evaluated using an emulator because evaluating the conditional submodel would decrease the efficiency of inter-processor communication, i.e., additional emulation steps are needed to evaluate a conditional submodel versus evaluating non-conditional submodels. The conditional submodel such as the one described has two possible results. The efficiency of inter-processor communication is decreased because calculation of the correct result requires extra emulation steps; further, the processors cannot calculate the result in parallel because the output of the first part of the equation, i.e., if (a!=0), is uncertain. Therefore, a compiler must convert the conditional submodel into a logically equivalent, but lengthier, non-conditional submodel. For example, if a, b, c and d are Boolean operands, the above sequence of operations may be rewritten as equation 2:b=a &(c+d)|!a &b   (2)
The above equation is a lengthier, logical non-conditional equivalent of the above conditional equation. The hardware emulator must evaluate the lengthier non-conditional equation even if the first part of the conditional statement it is based upon is likely to be false, i.e., the first part of the equation is not true and the remainder of the equation does not need to be evaluated.
Thus, there is a need in the art for a processor-based hardware emulation system capable of efficiently evaluating conditional submodels. The hardware emulation system should avoid evaluating submodels for which the conditions of execution are not satisfied.